250 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright ?intersil corporation 1999 hcs166ms radiation hardened 8-bit parallel-input/serial output shift register pinouts 16 lead ceramic dual-in-line metal seal package (sbdip) mil-std-1835 cdip2-t16, lead finish c top view 16 lead ceramic metal seal flatpack package (flatpack) mil-std-1835 cdfp4-f16, lead finish c top view ordering information part number temperature range screening level package HCS166DMSR -55 o c to +125 o c intersil class s equivalent 16 lead sbdip hcs166kmsr -55 o c to +125 o c intersil class s equivalent 16 lead ceramic flatpack hcs166d/ sample +25 o c sample 16 lead sbdip hcs166k/ sample +25 o c sample 16 lead ceramic flatpack hcs166hmsr +25 o c die die 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 d0 d1 d2 d3 ce gnd cp d7 q7 d6 d5 d4 pe ds vcc mr 2 3 4 5 6 7 8 116 15 14 13 12 11 10 9 d0 d1 d2 d3 ce gnd cp ds d7 q7 d6 d5 d4 pe vcc mr features 3 micron radiation hardened cmos sos total dose 200k rad (si) sep effective let no upsets: >100 mev-cm 2 /mg single event upset (seu) immunity < 2 x 10 -9 errors/ bit-day (typ) dose rate survivability: >1 x 10 12 rad (si)/s dose rate upset >10 10 rad s(si)/s 20ns pulse latch-up free under any conditions fanout (over temperature range) - standard outputs - 10 lsttl loads military temperature range: -55 o c to +125 o c signi?ant power reduction compared to lsttl ics dc operating voltage range: 4.5v to 5.5v input logic levels - vil = 0.3 vcc max - vih = 0.7 vcc min input current levels ii 5 a at vol, voh description the intersil hcs166ms is an 8-bit shift register that has fully synchronous serial or parallel data entry selected by an active low parallel enable (pe) input. when the pe is low one setup time before the low-to-high clock transition, parallel data is entered into the register. when pe is high, data is entered into internal bit position q0 from serial data input (ds), and the remaining bits are shifted one place to the right (q0 q1 q2m etc.) with each positive-going clock transition. for expansion of the register in parallel to serial converters, the q7 output is connected to the ds input of the succeeding stage. the clock input is a gated or structure which allows one input to be used as an active low clock enable (ce) input. the pin assignment for the cp and ce inputs is arbitrary and con be reversed for layout convenience. the low-to-high transition of ce input should only take place while the cp is high for predictable operation. a low on the master reset (mr) input overrides all other inputs and clears the register asynchronously, forcing all bit positions to a low state. the hcs166ms utilizes advanced cmos/sos technology to achieve high-speed operation. this device is a member of radiation hardened, high-speed, cmos/sos logic family. the hcs166ms is supplied in a 16 lead ceramic ?tpack (k suf?) or a sbdip package (d suf?). spec number 518758 file number 2482.2 september 1995
251 hcs166ms functional diagram truth table inputs internal q states output q7 master reset p arallel enable clock enable clock serial p arallel d0 - d7 q0 q1 l x xxx x l ll h x l l x x q00 q10 q0 h l l x a . . . h a b h h h l h x h q0n q6n h h l l x l q0n q6n h x h x x q00 q10 q70 h = high level l = low level x = immaterial = transition from low to high level a . . . h = the level of steady state input at inputs d0 thru d7, respectively. q00, q10, q70 = the level of q0, q1, or q7, respectively, before the indicated steady state input conditions were established. q0n, q6n = the level of q0 or q6, respectively, before the most recent transition of the clock. mr ce ds pe cp q7 d2 d0 d3 d5 d6 d7 d4 d1 spec number 518758
252 speci?ations hcs166ms absolute maximum ratings reliability information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7.0v input voltage range, all inputs . . . . . . . . . . . . .-0.5v to vcc +0.5v dc input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . 10ma dc drain current, any one output . . . . . . . . . . . . . . . . . . . . . . . 25ma (all voltage reference to the vss terminal) storage temperature range (tstg) . . . . . . . . . . . -65 o c to +150 o c lead temperature (soldering 10sec) . . . . . . . . . . . . . . . . . . +265 o c junction temperature (tj) . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c esd classi?ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance ja jc sbdip package. . . . . . . . . . . . . . . . . . . . 73 o c/w 24 o c/w ceramic flatpack package . . . . . . . . . . . 114 o c/w 29 o c/w maximum package power dissipation at +125 o c ambient sbdip package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68w ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44w if device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: sbdip package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mw/ o c ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . . 8.8mw/ o c caution: as with all semiconductors, stress listed under ?bsolute maximum ratings?may be applied to devices (one at a time) w ithout resulting in permanent damage. this is a stress rating only. exposure to absolute maximum rating conditions for extended periods may affect device rel iability. the conditions listed under ?lectrical performance characteristics?are the only conditions recommended for satisfactory device operation. operating conditions supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v input rise and fall times at 4.5v vcc (tr, tf) . . . . . . .500ns max operating temperature range (t a ) . . . . . . . . . . . . -55 o c to +125 o c input low voltage (vil). . . . . . . . . . . . . . . . . . . 0.0v to 30% of vcc input high voltage (vih) . . . . . . . . . . . . . . . . . . 70% of vcc to vcc table 1. dc electrical performance characteristics parameter symbol (note 1) conditions group a sub- groups temperature limits units min max quiescent current icc vcc = 5.5v, vin = vcc or gnd 1 +25 o c-40 a 2, 3 +125 o c, -55 o c - 750 a output current (sink) iol vcc = 4.5v, vih = 4.5v, vout = 0.4v, vil = 0v 1 +25 o c 4.8 - ma 2, 3 +125 o c, -55 o c 4.0 - ma output current (source) ioh vcc = 4.5v, vih = 4.5v, vout = vcc -0.4v, vil = 0v 1 +25 o c -4.8 - ma 2, 3 +125 o c, -55 o c -4.0 - ma output voltage low vol vcc = 4.5v, vih = 3.15v, iol = 50 a, vil = 1.35v 1, 2, 3 +25 o c, +125 o c, -55 o c - 0.1 v vcc = 5.5v, vih = 3.85v, iol = 50 a, vil = 1.65v 1, 2, 3 +25 o c, +125 o c, -55 o c - 0.1 v output voltage high voh vcc = 4.5v, vih = 3.15v, ioh = -50 a, vil = 1.35v 1, 2, 3 +25 o c, +125 o c, -55 o c vcc -0.1 -v vcc = 5.5v, vih = 3.85v, ioh = -50 a, vil = 1.65v 1, 2, 3 +25 o c, +125 o c, -55 o c vcc -0.1 -v input leakage current iin vcc = 5.5v, vin = vcc or gnd 1 +25 o c- 0.5 a 2, 3 +125 o c, -55 o c- 5.0 a noise immunity functional test fn vcc = 4.5v, vih = 0.70(vcc), vil = 0.30(vcc), (note 2) 7, 8a, 8b +25 o c, +125 o c, -55 o c--- notes: 1. all voltages reference to device gnd. 2. for functional tests, vo 4.0v is recognized as a logic ?? and vo 0.5v is recognized as a logic ?? spec number 518758
253 speci?ations hcs166ms table 2. ac electrical performance characteristics parameter symbol (notes 1, 2) conditions group a sub- groups temperature limits units min max cp or ce to q7 tphl tplh vcc = 4.5v 9 +25 o c 2 32 ns 10, 11 +125 o c, -55 o c 2 37 ns mr to q7 tphl vcc = 4.5v 9 +25 o c 2 31 ns 10, 11 +125 o c, -55 o c 2 36 ns notes: 1. all voltages referenced to device gnd. 2. ac measurements assume rl = 500 ? , cl = 50pf, input tr = tf = 3ns, vil = gnd, vih = vcc. table 3. electrical performance characteristics parameter symbol (note 1) conditions temperature limits units min max capacitance power dissipation cpd vcc = 5.0v, f = 1mhz +25 o c - 65 pf +125 o c, -55 o c - 81 pf input capacitance cin vcc = 5.0v, f = 1mhz +25 o c - 10 pf +125 o c - 10 pf output transition time (figure 1) tthl ttlh vcc = 4.5v +25 o c - 15 ns +125 o c, -55 o c - 22 ns clock frequency (figure 1) fmax vcc = 4.5v +25 o c 30 - mhz -55 o c to +125 o c 20 - mhz mr pulse width (figure 2) tw vcc = 4.5v +25 o c20-ns -55 o c to +125 o c30-ns clock pulse width (figure 1) tw vcc = 4.5v +25 o c16-ns -55 o c to +125 o c24-ns set-up time data and ce to clock, (figure 3, 4) tsu vcc = 4.5v +25 o c16-ns -55 o c to +125 o c24-ns hold time data to clock (figure 4) th vcc = 4.5v +25 o c1-ns -55 o c to +125 o c1-ns removal time mr to clock (figure 3) trem vcc = 4.5v +25 o c0-ns -55 o c to +125 o c0-ns set-up time pe to cp (figure 4) tsu vcc = 4.5v +25 o c29-ns -55 o c to +125 o c44-ns hold time pe to cp or ce (figure 4) th vcc = 4.5v +25 o c0-ns -55 o c to +125 o c0-ns note: 1. the parameters listed in table 3 are controlled via design or process parameters. min and max limits are guaranteed but not d irectly tested. these parameters are characterized upon initial design release and upon design changes which affect these characteristi cs. spec number 518758
254 speci?ations hcs166ms table 4. dc post radiation electrical performance characteristics parameter symbol (notes 1, 2) conditions temperature 200k rad limits units min max quiescent current icc vcc = 5.5v, vin = vcc or gnd +25 o c - 0.75 ma output current (sink) iol vcc = 4.5v, vin = vcc or gnd, vout = 0.4v +25 o c 4.0 - ma output current (source) ioh vcc = 4.5v, vin = vcc or gnd, vout = vcc -0.4v +25 o c -4.0 - ma output voltage low vol vcc = 4.5v and 5.5v, vih = 0.70(vcc), vil = 0.30(vcc), iol = 50 a +25 o c - 0.1 v output voltage high voh vcc = 4.5v and 5.5v, vih = 0.70(vcc), vil = 0.30(vcc), ioh = -50 a +25 o c vcc -0.1 -v input leakage current iin vcc = 5.5v, vin = vcc or gnd +25 o c- 5 a noise immunity functional test fn vcc = 4.5v, vih = 0.70(vcc), vil = 0.30(vcc), (note 3) +25 o c --- cp or ce to q7 tphl vcc = 4.5v +25 o c 2 37 ns tplh vcc = 4.5v +25 o c 2 37 ns mr to q7 tphl vcc = 4.5v +25 o c 2 36 ns notes: 1. all voltages referenced to device gnd. 2. ac measurements assume rl = 500 ? , cl = 50pf, input tr = tf = 3ns, vil = gnd, vih = vcc. 3. for functional tests, vo 4.0v is recognized as a logic ?? and vo 0.5v is recognized as a logic ?? table 5. burn-in and operating life test, delta parameters (+25 o c) parameter group b subgroup delta limit icc 5 12 a iol/ioh 5 -15% of 0 hour spec number 518758
255 speci?ations hcs166ms table 6. applicable subgroups conformance groups method group a subgroups read and record initial test (preburn-in) 100%/5004 1, 7, 9 icc, iol/h interim test i (postburn-in) 100%/5004 1, 7, 9 icc, iol/h interim test ii (postburn-in) 100%/5004 1, 7, 9 icc, iol/h pda 100%/5004 1, 7, 9, deltas interim test iii (postburn-in) 100%/5004 1, 7, 9 icc, iol/h pda 100%/5004 1, 7, 9, deltas final test 100%/5004 2, 3, 8a, 8b, 10, 11 group a (note 1) sample/5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 group b subgroup b-5 sample/5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11, deltas subgroups 1, 2, 3, 9, 10, 11, (note 2) subgroup b-6 sample/5005 1, 7, 9 group d sample/5005 1, 7, 9 notes: 1. alternate group a testing in accordance with method 5005 of mil-std-883 may be exercised. 2. table 5 parameters only. table 7. total dose irradiation conformance groups method test read and record pre rad post rad pre rad post rad group e subgroup 2 5005 1, 7, 9 table 4 1, 9 table 4 (note 1) note: 1. except fn test which will be performed 100% go/no-go. table 8. static and dynamic burn-in test connections open ground 1/2 vcc = 3v 0.5v vcc = 6v 0.5v oscillator 50khz 25khz static i burn-in (note 1) 13 1 - 12, 14 - 15 - 16 - - static ii burn-in (note 1) 13 8 - 1 - 7, 9 - 12, 14 - 16 - - dynamic burn-in (note 2) - 2, 4, 6, 8, 10, 12 13 3, 5, 9, 11, 14 - 16 7 1 notes: 1. each pin except vcc and gnd will have a resistor of 10k ? 5% for static burn-in 2. each pin except vcc and gnd will have a resistor of 1k ? 5% for dynamic burn-in table 9. irradiation test connections open ground vcc = 5v 0.5v 13 8 1 - 7, 9 - 12, 14 - 16 note: each pin except vcc and gnd will have a resistor of 47k ? 5% for irradiation testing. group e, subgroup 2, sample size is 4 dice/wafer 0 failures. spec number 518758
256 hcs166ms intersil space level product flow - ?s wafer lot acceptance (all lots) method 5007 (includes sem) gamma radiation veri?ation (each wafer) method 1019, 4 samples/wafer, 0 rejects 100% nondestructive bond pull, method 2023 sample - wire bond pull monitor, method 2011 sample - die shear monitor, method 2019 or 2027 100% internal visual inspection, method 2010, condition a 100% temperature cycle, method 1010, condition c, 10 cycles 100% constant acceleration, method 2001, condition per method 5004 100% pind, method 2020, condition a 100% external visual 100% serialization 100% initial electrical test (t0) 100% static burn-in 1, condition a or b, 24 hrs. min., +125 o c min., method 1015 100% interim electrical test 1 (t1) 100% delta calculation (t0-t1) 100% static burn-in 2, condition a or b, 24 hrs. min., +125 o c min., method 1015 100% interim electrical test 2 (t2) 100% delta calculation (t0-t2) 100% pda 1, method 5004 (notes 1and 2) 100% dynamic burn-in, condition d, 240 hrs., +125 o c or equivalent, method 1015 100% interim electrical test 3 (t3) 100% delta calculation (t0-t3) 100% pda 2, method 5004 (note 2) 100% final electrical test 100% fine/gross leak, method 1014 100% radiographic, method 2012 (note 3) 100% external visual, method 2009 sample - group a, method 5005 (note 4) 100% data package generation (note 5) notes: 1. failures from interim electrical test 1 and 2 are combined for determining pda 1. 2. failures from subgroup 1, 7, 9 and deltas are used for calculating pda. the maximum allowable pda = 5% with no more than 3% o f the failures from subgroup 7. 3. radiographic (x-ray) inspection may be performed at any point after serialization as allowed by method 5004. 4. alternate group a testing may be performed as allowed by mil-std-883, method 5005. 5. data package contents: cover sheet (intersil name and/or logo, p.o. number, customer part number, lot date code, intersil part number, lot number, quantity). wafer lot acceptance report (method 5007). includes reproductions of sem photos with percent of step coverage. gamma radiation report. contains cover page, disposition, rad dose, lot number, test package used, speci?ation numbers, test equipment, etc. radiation read and record data on ?e at intersil. x-ray report and ?m. includes penetrometer measurements. screening, electrical, and group a attributes (screening attributes begin after package seal). lot serial number sheet (good units serial number and lot number). variables data (all delta operations). data is identi?d by serial number. data header includes lot number and date of test. the certi?ate of conformance is a part of the shipping invoice and is not part of the data book. the certi?ate of conformanc e is signed by an authorized quality representative. spec number 518758
257 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?ations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com hcs166ms spec number 518758 ac timing diagrams and ac load circuit figure 1. clock pre-requisite times and propaga- tion and output transition times figure 2. master resit pre-requisite times and propagation delays. figure 3. data pre-requisite times figure 4. parallel enable or clock enable pre- requisite times figure 5. ac load circuit tw vs 50 vs input level gnd tthl vs vs tphl tplh ttlh t/f max tf tr tw vs vs input level gnd tphl vs trem vs mr cp q7 input level gnd vs valid data input gnd cp tsu th vs level input level gnd valid level gnd pe or ce tsu th vs input level input gnd vs ac voltage levels parameter hcs units vcc 4.50 v vih 4.50 v vs 2.25 v vil 0 v gnd 0 v dut test cl rl point cl = 50pf rl = 500 ?
258 hcs166ms die characteristics die dimensions: 94 x 94 mils metallization: type: alsi metal thickness: 11k ? 1k ? glassivation: type: sio 2 thickness: 13k ? 2.6k ? worst case current density: < 2.0 x 10 5 a/cm 2 bond pad size: 100 m x 100 m 4 mils x 4 mils metallization mask layout hcs166ms note: the die diagram is a generic plot from a similar hcs device. it is intended to indicate approximate die size and bond pad location. the mask series for the hcs166 is ta14386a. ds (1) d0 d1 (3) (2) d2 (4) d3 (5) ce (6) (7) cp (8) gnd (9) mr (10) d4 (11) d5 vcc (16) pe (15) (14) d7 (13) q7 (12) d6 spec number 518758
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